Preparation of Nanoporous Silicon

Report No. ARl-TR-4306
Authors: Wayne A. Churaman and Luke Currano
Date/Pages: October 2007; 22 pages
Abstract: While research has focused on the optical properties of nanoporous silicon and its use as an isolation material in integrated circuits, there is a great deal to be gained by understanding the formation process of such a versatile material. The structure itself is made up of millions of pores that are formed through an electrochemical wet etch, which results in network clusters of nanoporous material with a surface area on the order of 50 m2/g. In this report, we explore the process of preparing the nanoporous silicon, while presenting solutions to some of the challenges that arise during the pore formation. These challenges include cracking of the nanoporous layer when attempting to etch pores with a vertical depth greater than ~35 µm, as well as effects of electric field concentrations in the etch process, which degrade structural integrity. In addition we provide a quantitative analysis of the material's structural layer and present an alternative approach to the current wet etching technique.
Distribution: Approved for public release
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Last Update / Reviewed: October 1, 2007