Full Custom Integrated Circuit (IC) Design Flow at U.S. Army Research Laboratory

Report No. ARL-TN-0422
Authors: James Wilson
Date/Pages: February 2011; 28 pages
Abstract: The steps required to set up and run the Cadence Full Custom Integrated Circuit Design Flow are given in detail. Included is a walkthrough showing the design of an inverter, from schematic capture through layout, including design rule check (DRC), layout versus schematic (LVS) and parasitic extraction.
Distribution: Approved for public release
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Last Update / Reviewed: February 1, 2011