Using Loop-Level Parallelism to Parallelize Vectorizable Programs

Report No. ARL-TR-2556
Authors: Daniel M. Pressel, Jubaraj Sahu and Karen R. Heavey
Date/Pages: August 2001; 42 pages
Abstract: One of the major challenges facing "high performance computing" is the daunting task of producing programs that achieve acceptable levels of performance when RUN on parallel architectures. Although many organizations have been activelly working in this area for some time, many programs have yet to become parallelized. Furthermore, some programs that were parallelized were done so for obsolete systems. These programs may run poorly, if at all, on the current generation of parallel computers. Therefore, a straightforward approach to parallelizing vectorizable codes is needed without introducing any changes to the algorithm or the convergence properties of the codes. Using the combination of loop-level parallelism and RISC-based shared memory SMPs has proven to be a successful approach to solving this problem.
Distribution: Approved for public release
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Last Update / Reviewed: August 1, 2001